Intel Core Ultra 7 255H vs Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)
No like-for-like comparison yet: both have published results, but model size or batch differ. Treat the numbers below as indicative only.
| Intel Core Ultra 7 255H | Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) | |
|---|---|---|
| Best LLM generation | 115 tok/s D 2026-10-01 (published) | n/a |
| Power | n/a | n/a |
| Perf / W | n/a | n/a |
| Price | n/a | n/a |
| Workloads with data | 1 of 7 | 3 of 7 |
Best published LLM generation result per platform. n/a = not published; never estimated.
Show data — all workloads, sources and like-for-like groups
object detection
Only Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) has published object detection results.
| Platform | Result | Model · precision · stack | Grade | Power | Source |
|---|---|---|---|---|---|
| Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) | 117 FPS throughput · b=1 | yolo-v3-tiny-tf FP16 · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · unknown | D | unknown power n/a no power published | Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published) |
Intel Core Ultra 7 255H:
No published object detection results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
instance segmentation
No published instance segmentation results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
pose estimation
No published pose estimation results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
image classification
Only Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) has published image classification results.
| Platform | Result | Model · precision · stack | Grade | Power | Source |
|---|---|---|---|---|---|
| Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) | 1391 FPS throughput · b=1 | mobilenet-v1-1.0-224 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mobile-class CNN | D | unknown power n/a no power published | Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published) |
Intel Core Ultra 7 255H:
No published image classification results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
semantic segmentation
Only Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) has published semantic segmentation results.
| Platform | Result | Model · precision · stack | Grade | Power | Source |
|---|---|---|---|---|---|
| Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) | 10.26 FPS throughput · b=1 | unet-camvid-onnx-0001 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mid-size CNN | D | unknown power n/a no power published | Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published) |
Intel Core Ultra 7 255H:
No published semantic segmentation results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
speech-to-text
No published speech-to-text results for Intel Core Ultra 7 255H or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
LLM generation
Only Intel Core Ultra 7 255H has published LLM generation results.
| Platform | Result | Model · precision · stack | Grade | Power | Source |
|---|---|---|---|---|---|
| Intel Core Ultra 7 255H | 110 tok/s 2nd-token throughput, input 32 tokens · b=1 | minicpm4-0.5b INT4-MIXED · OpenVINO 2026.4.1 GenAI · LLM ≤4B | D | unknown power n/a no power published | OpenVINO official LLM benchmarks (llm_models_7-255H.csv) 2026-10-01 (published) |
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite):
No published LLM generation results for Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) or Intel Core Ultra 7 255H yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.
How to read these numbers
Machine-readable: /find.json (see llms.txt); full tables are in “Show data”. Confidence grades: A audited MLPerf closed · B documented third-party · C community · D vendor-published · E estimate. Unknown values are shown as unknown, never estimated. Generated 2026-10-16 from public sources.