Edge-AI chip rumors and leaks (unconfirmed, sourced)
These are leaks and rumors, not HWBench data. Nothing on this page is used in our rankings, tables or platform pages. Each item is dated, labelled, summarised in our own words and linked to its sources. Items marked Confirmed by vendor were stated by the vendor itself. Numbers enter HWBench only once measured, sourced results are published.
An XDA hands-on investigation found the RTX Spark NPU behaves like a descendant of NVIDIA's Deep Learning Accelerator used in Jetson Orin, and got ResNet-50 running on it. The reported NPU rating is 50-55 TOPS, but the tester could not exceed about 6 TOPS in INT8 or FP16 with current beta software. NVIDIA has not confirmed the architecture.
Why it matters for edge AI: Direct: an NPU tied to Jetson's DLA lineage, with early independent measurements. These are a single tester's results on beta software and are not in our rankings.
NPU is a DLA-family block (unconfirmed)
~6 TOPS reached vs 50-55 TOPS quoted (disputed)
Caveat: Independent reverse-engineering on beta tools; NVIDIA says a white paper will follow.
A Geekbench 7 entry for the 256-core EPYC 9996 (Zen 6c) scored 2,847 single-core at about 4.1 GHz. A user-run Ryzen 7 9700X fixed at 4.1 GHz scored 2,444, about 16.5% lower. A separate per-GHz comparison against a 5.5 GHz EPYC 4545P gives roughly 23-24%, but across different clocks and platforms.
Why it matters for edge AI: Indirect: these are general CPU scores, not AI results. Zen 6 cores are expected in AMD's next mobile APUs (Medusa Point) alongside an NPU; we will add AI benchmarks only when measured results are published.
About 16.5% higher Geekbench 7 single-core score than Zen 5 at ~4.1 GHz (unconfirmed)
Up to ~24% per-clock gain (cross-clock normalisation, different platforms) (unconfirmed)
Caveat: Zen 6c server core vs Zen 5 desktop core, different memory and platforms; the original Geekbench entry was reported removed. Not a direct IPC measurement.
HIP-RT 3.2.0 adds support for GFX1170, GFX1171 and GFX115E, which reports tie to Zen 6 Medusa APUs. Earlier leaks place GFX117x on RDNA 4m and GFX115x on RDNA 3.5, suggesting mixed iGPU generations across Medusa models.
Why it matters for edge AI: Indirect: iGPU identifiers only; no NPU details for Medusa have leaked.
GFX1170/1171/115E belong to Medusa APUs (unconfirmed)
Mix of RDNA 4m and RDNA 3.5 iGPUs across Medusa (unconfirmed)
Caveat: Inferred from software IDs; AMD has not described the parts.
Jaykihn says the 4995HX uses 8 P-cores, 16 E-cores, 4 LP E-cores and 2 Xe3 GPU cores, and the 4970H uses 4+8+4 cores with a 12-core Xe3P iGPU. The HX compute tile on TSMC N2P is put at about 98 mm².
Why it matters for edge AI: Indirect: CPU/iGPU configuration; the 12-core Xe3P iGPU could matter for GPU-side local inference, but no AI figures were given.
4995HX 8P+16E+4LPE, 2 Xe3 cores (unconfirmed)
4970H 4+8+4 with 12 Xe3P cores (unconfirmed)
Caveat: Clocks, cache and power unknown; laptop timing around CES 2027 is tentative.
Overclocker 1usmus posted that a 12-core, one-CCD Zen 6 desktop chip gets 'surprisingly close' to current 16-core Zen 5 parts in Cinebench multi-thread. No score, screenshot or test setup was published.
Why it matters for edge AI: Indirect: CPU multi-thread claim only; no NPU or AI workload involved.
12-core Zen 6 near 16-core Zen 5 in Cinebench multi-thread (unconfirmed)
Caveat: A claim without published data; the report itself notes it is not a leaked result.
Jaykihn retracted an earlier claim and said H and suffix-less mobile Nova Lake chips also use the four-digit Core Ultra 4000 naming, so all five families would share it.
Why it matters for edge AI: Indirect: branding only; no AI data.
All Nova Lake families named Core Ultra 4000 (unconfirmed)
Moore's Law Is Dead shared Nova Lake-H/HX die shots showing a six-tile layout: compute tiles on TSMC N2P (about 104 mm² for 8P+16E), SoC and peripheral tiles on Intel 18A-P, and a GPU tile of up to 12 Xe3P cores.
Why it matters for edge AI: Indirect: packaging and process details; no NPU or AI figures.
A specification table on Decenta's M26-NVLS-ATX09 motherboard page lists Nova Lake AI throughput as 73 TOPS for the NPU, 39 for the CPU and 25 for the Xe3 GPU. Intel's current Arrow Lake desktop NPU is rated 13 TOPS. Intel has not confirmed the figure, and the precision is not stated.
Why it matters for edge AI: Direct: a desktop NPU in this class would exceed the 40 TOPS Copilot+ minimum and be a new local-inference target.
NPU 73 TOPS, CPU 39, GPU 25 (precision not stated) (unconfirmed)
Caveat: Third-party board listing, not an Intel specification. TOPS is a peak figure, not a benchmark.
Screenshots from a Qualcomm reference device showed a 2+3+3 CPU layout peaking at 5,068 MHz and an Adreno 850 GPU. Qualcomm has since announced the chip.
Why it matters for edge AI: Indirect: CPU/GPU details only; the leak had no NPU figures.
2+3+3 CPU up to 5,068 MHz, Adreno 850 (unconfirmed)
Caveat: Pre-production unit; final specs are per Qualcomm's announcement.
Confirmed by AMD: Ryzen 'Olympic Ridge' (Zen 6) desktop CPUs use socket AM5
Confirmed by vendor AMD · Reported · added 2026-10-24
AMD updated its technical documentation to list Olympic Ridge (Zen 6) desktop processors as AM5-compatible; AMD had earlier said AM5 is supported through 2029. The same page also lists 'Medusa1' for AM5, which suggests a socketed Medusa APU, but that part is an interpretation.
Why it matters for edge AI: Indirect: platform news. A socketed Medusa APU would bring an NPU to AM5 desktops, which is not confirmed.
Zen 6 'Olympic Ridge' is AM5-compatible (confirmed)
A Geekbench entry for an unannounced AMD chip on a 'Plum-MDS1' platform showed 10 cores / 20 threads and 32 MB L3, running mostly near 1.4 GHz as an early engineering sample. The scores are not meaningful at those clocks.
Why it matters for edge AI: Direct: Medusa Point is AMD's next laptop APU and is expected to carry an updated NPU, so it is a future edge-AI/AI-PC target. No NPU figure has leaked.
10 cores, 32 MB L3 on an early sample (unconfirmed)
Leaker HXL listed the Zen 6 CCD as 12 cores with 48 MB of shared L3 on TSMC N2, at about 76 mm² (Zen 5: 8 cores, 32 MB, ~71 mm²). AMD has not confirmed the core count, cache or die size.
Why it matters for edge AI: Indirect: larger L3 can help CPU-side inference and pre/post-processing, but no AI data is involved.