Google Coral Dev Board (Edge TPU) vs Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)

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Showing the newest results per platform and source. 18 superseded older results are hidden.Showing all results, including 18 superseded by newer results from the same source.

Google Coral Dev Board (Edge TPU) is faster in the only like-for-like comparison (largest gap: semantic segmentation, 17.10×).

	Google Coral Dev Board (Edge TPU)	Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)
Best semantic segmentation	175 FPS D Older data (2020)	10.26 FPS D 2026-08-10 (published)
Power	2.00 W spec	n/a
Perf / W	87.72 FPS/W spec	n/a
Price	n/a	n/a
Workloads with data	1 of 7	3 of 7

Best published semantic segmentation result per platform (may be from different like-for-like groups — see data). n/a = not published; never estimated.

Show data — all workloads, sources and like-for-like groups

object detection

Only Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) has published object detection results.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	117 FPS throughput · b=1	yolo-v3-tiny-tf FP16 · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · unknown	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

Google Coral Dev Board (Edge TPU):

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No published object detection results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

instance segmentation

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No published instance segmentation results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

pose estimation

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No published pose estimation results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

image classification

Only Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) has published image classification results.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	1391 FPS throughput · b=1	mobilenet-v1-1.0-224 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mobile-class CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

Google Coral Dev Board (Edge TPU):

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No published image classification results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

semantic segmentation

✓ Like-for-like: model-size class mid-size CNN, batch 1. Model, precision and stack may still differ.

Platform	Result	Model · precision · stack	Grade	Power	Source
Google Coral Dev Board (Edge TPU)	175 FPS inference_time · b=1	Unet Mv2 (128x128) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · mid-size CNN	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2020)
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	10.26 FPS throughput · b=1	unet-camvid-onnx-0001 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mid-size CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

speech-to-text

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No published speech-to-text results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

LLM generation

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No published LLM generation results for Google Coral Dev Board (Edge TPU) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

Split result: Google Coral Dev Board (Edge TPU) is faster in 1 and Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) in 3 of 4 like-for-like comparisons.

	Google Coral Dev Board (Edge TPU)	Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)
Best image classification	500 FPS D Older data (2019)	1391 FPS D 2026-08-10 (published)
Power	2.00 W spec	n/a
Perf / W	250 FPS/W spec	n/a
Price	n/a	n/a
Workloads with data	3 of 7	3 of 7

Best published image classification result per platform (may be from different like-for-like groups — see data). n/a = not published; never estimated.

Show data — all workloads, sources and like-for-like groups

object detection

⚠ MIXED COMPARISON — not like-for-like. Baseline mobile-class CNN at batch 1. Differs: model-size class unknown vs mobile-class CNN.

Platform	Result	Model · precision · stack	Grade	Power	Source
Google Coral Dev Board (Edge TPU)	90.91 FPS inference_time · b=1	MobileNet v1 SSD (224x224) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · mobile-class CNN	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2019)
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) MIXED: model-size class unknown vs mobile-class CNN	117 FPS throughput · b=1	yolo-v3-tiny-tf FP16 · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · unknown	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

No shared like-for-like group exists for this pair.

instance segmentation

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pose estimation

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image classification

✓ Like-for-like: model-size class mid-size CNN, batch 1. Model, precision and stack may still differ.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	220 FPS throughput · b=1	resnet-50-tf not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mid-size CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)
Google Coral Dev Board (Edge TPU)	17.86 FPS inference_time · b=1	ResNet-50 V1 (299x299) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · mid-size CNN	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2019)

✓ Like-for-like: model-size class mobile-class CNN, batch 1. Model, precision and stack may still differ.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	1391 FPS throughput · b=1	mobilenet-v1-1.0-224 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mobile-class CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)
Google Coral Dev Board (Edge TPU)	417 FPS inference_time · b=1	MobileNet v1 (224x224) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · mobile-class CNN	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2019)

✓ Like-for-like: model-size class unknown, batch 1 (size or batch not stated by source — unverified). Model, precision and stack may still differ.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	1289 FPS throughput · b=1	yolo-v8-nano classification not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · unknown	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)
Google Coral Dev Board (Edge TPU)	500 FPS inference_time · b=1	SqueezeNet (224x224) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · unknown	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2019)

semantic segmentation

✓ Like-for-like: model-size class mid-size CNN, batch 1. Model, precision and stack may still differ.

Platform	Result	Model · precision · stack	Grade	Power	Source
Google Coral Dev Board (Edge TPU)	175 FPS inference_time · b=1	Unet Mv2 (128x128) INT8 · TensorFlow Lite C++ benchmark (Edge TPU runtime) · mid-size CNN	D	2.00 W spec platform spec envelope (not measured with this result)	Google Coral Edge TPU benchmarks page (Table 1) Older data (2020)
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	10.26 FPS throughput · b=1	unet-camvid-onnx-0001 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mid-size CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

speech-to-text

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LLM generation

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How to read these numbers

Every number is labelled. Confidence: A MLPerf closed, audited · B documented third-party method · C community / review · D vendor-published, not independently verified · E estimate. Power basis: measured with the result · spec vendor spec/envelope · power n/a not published.

Machine-readable: /find.json (see llms.txt); full tables are in “Show data”. Confidence grades: A audited MLPerf closed · B documented third-party · C community · D vendor-published · E estimate. Unknown values are shown as unknown, never estimated. Generated 2026-10-16 from public sources.