AMD Zynq UltraScale+ ZCU102 (ZU9EG) vs Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)

FPGA / Versal coverage note: 1,243 rows come from the AMD Vitis AI 3.0/3.5 Model Zoo tables; 733 (59%) are image classification. Detection, segmentation and other workloads are thinner, and there is no LLM or speech data for these boards. All are vendor-published (grade D). FPGA / Versal overview.

AMDeval kit (adaptive SoC)No licensed photo yet

AlteraFPGA (PCIe/dev kit)No licensed photo yet

No like-for-like comparison yet: both have published results, but model size or batch differ. Treat the numbers below as indicative only.

	AMD Zynq UltraScale+ ZCU102 (ZU9EG)	Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)
Best object detection	539 FPS D Older data (2023)	117 FPS D 2026-08-10 (published)
Power	n/a	n/a
Perf / W	n/a	n/a
Price	n/a	n/a
Workloads with data	4 of 7	3 of 7

Best published object detection result per platform. n/a = not published; never estimated.

Show data — all workloads, sources and like-for-like groups

object detection

⚠ MIXED COMPARISON — not like-for-like. Baseline small (YOLO-s) at batch unknown. Differs: model-size class unknown vs small (YOLO-s); batch 1 vs unknown.

Platform	Result	Model · precision · stack	Grade	Power	Source
AMD Zynq UltraScale+ ZCU102 (ZU9EG)	26.09 FPS E2E throughput, multi thread · b=unknown	pt_yolov5s6_coco_1280_1280_17G INT8 · Vitis AI 3.0 (VART) · small (YOLO-s)	D	unknown power n/a no power published	Vitis AI 3.0 Model Zoo performance table Older data (2023)
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) MIXED: model-size class unknown vs small (YOLO-s); batch 1 vs unknown	117 FPS throughput · b=1	yolo-v3-tiny-tf FP16 · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · unknown	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)

No shared like-for-like group exists for this pair.

instance segmentation

◌

No published instance segmentation results for AMD Zynq UltraScale+ ZCU102 (ZU9EG) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

pose estimation

Only AMD Zynq UltraScale+ ZCU102 (ZU9EG) has published pose estimation results.

Platform	Result	Model · precision · stack	Grade	Power	Source
AMD Zynq UltraScale+ ZCU102 (ZU9EG)	391 FPS E2E throughput, multi thread · b=unknown	pt_movenet_coco_192_192_0.5G INT8 · Vitis AI 3.0 (VART) · mobile-class CNN	D	unknown power n/a no power published	Vitis AI 3.0 Model Zoo performance table Older data (2023)

Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite):

◌

No published pose estimation results for Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) or AMD Zynq UltraScale+ ZCU102 (ZU9EG) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

image classification

⚠ MIXED COMPARISON — not like-for-like. Baseline mobile-class CNN at batch 1. Differs: batch unknown vs 1.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	1391 FPS throughput · b=1	mobilenet-v1-1.0-224 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mobile-class CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)
AMD Zynq UltraScale+ ZCU102 (ZU9EG) MIXED: batch unknown vs 1	4832 FPS E2E throughput, multi thread · b=unknown	tf_mobilenetv1_0.25_imagenet_128_128_27M INT8 · Vitis AI 3.0 (VART) · mobile-class CNN	D	unknown power n/a no power published	Vitis AI 3.0 Model Zoo performance table Older data (2023)

No shared like-for-like group exists for this pair.

semantic segmentation

⚠ MIXED COMPARISON — not like-for-like. Baseline mid-size CNN at batch 1. Differs: batch unknown vs 1.

Platform	Result	Model · precision · stack	Grade	Power	Source
Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite)	10.26 FPS throughput · b=1	unet-camvid-onnx-0001 not stated in table (set by .arch file) · FPGA AI Suite 2026.1.1 / OpenVINO; IP throughput (hostless) · mid-size CNN	D	unknown power n/a no power published	Altera FPGA AI Suite Handbook (performance tables) 2026-08-10 (published)
AMD Zynq UltraScale+ ZCU102 (ZU9EG) MIXED: batch unknown vs 1	437 FPS E2E throughput, multi thread · b=unknown	tf2_2d-unet_nuclei_128_128_5.31G INT8 · Vitis AI 3.0 (VART) · mid-size CNN	D	unknown power n/a no power published	Vitis AI 3.0 Model Zoo performance table Older data (2023)

No shared like-for-like group exists for this pair.

speech-to-text

◌

No published speech-to-text results for AMD Zynq UltraScale+ ZCU102 (ZU9EG) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

LLM generation

◌

No published LLM generation results for AMD Zynq UltraScale+ ZCU102 (ZU9EG) or Terasic DE10-Agilex Development Board (Agilex 7, FPGA AI Suite) yet.
We only show cited public figures — nothing is estimated to fill gaps. Requests tell us what to source or test next.

How to read these numbers

Every number is labelled. Confidence: A MLPerf closed, audited · B documented third-party method · C community / review · D vendor-published, not independently verified · E estimate. Power basis: measured with the result · spec vendor spec/envelope · power n/a not published.

Machine-readable: /find.json (see llms.txt); full tables are in “Show data”. Confidence grades: A audited MLPerf closed · B documented third-party · C community · D vendor-published · E estimate. Unknown values are shown as unknown, never estimated. Generated 2026-10-16 from public sources.